Character font generating system for cathode-ray tube displays, or the like

ABSTRACT

A character generating system is provided which responds to multi-bit digital commands derived, for example, from a read-only memory, for generating analog signals suitable for controlling the beam of a cathode-ray tube so as to cause characters and symbols to be formed on the viewing screen of the cathode-ray tube. The system to be described is capable, for example, of producing four distinct figures, and these figures are combined to define the selected characters and symbols on the cathode-ray tube screen. The production of part or all of any one of the four distinct figures will be defined herein as a &#39;&#39;&#39;&#39;draw&#39;&#39;&#39;&#39;, and any standard alpha-numeric character and other symbols may be implemented in three draws or less. The individual figures are produced in the system by analog function generators, and the function generators and appropriate blanking circuitry are controlled in accordance with the commands to cause the cathoderay tube to produce the desired symbols and characters.

United States Patent mi Hasenbalg [45] Jan. 16,1973

[54! CHARACTER FONT GENERATING Irimarv Examiner-David ln 'l'ral'lon SYSTEM FOR CATHODE-RAY TUBE Attorney-Robert Louis Finkel DISPLAYS, OR THE LIKE {57] ABSTRACT [75] Inventor: Ralph D. Hasenbalg, Canoga Park,

C lif. A character generating system is provided which v c I I C P k responds to multi-hit digital commands derived, for Amgnu' r s" example, lrom a read-only memory, lor generating analog signals suitable for controlling the beam of a [22] Filed: March 8, 1971 cathode-ray tube so as to cause characters and symbols to be formed on the viewing screen of the [211 App. 122957 cathode-ray tube. The system to be described is capable, for example, of producing four distinct figures, [52] US. Cl. .340/324 A, 315/18 and these figures are combined to define the selected [51] Int. Cl. ..G06 3/14 characters and symbols on the cathoderay tube [58] Field of Search ..340/324 A screen. The production of part or all of any one of the four distinct figures will be defined herein as a [56] References Cited draw", and any standard alpha-numeric character and ATENTS other symbols may be implemented in three draws or UNITED STATES P less. The individual figures are produced in the system $335,416 8/l967 Hughes ..340 324 A y analog function g r n h function 3329948 7/1967 Halsted 4. 340/324 A generators and appropriate blanking circuitry are con- 5 6 Yanishevsky 40/ A X trolled in accordance with the commands to cause the 3,63l,456 12/1971 Yokoyama ..34()/324 A cathodeqay tube to produce the desired Symbols and characters.

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(54 (660 (6-1,! (Gt/ f PATENTEDJAH 16 1975 sum 2 BF 5 PATENTEUJAN 16 ms SHEET 3 BF 5 M a/vraz CHARACTER FONT GENERATING SYSTEM FOR CATHODE-RAY TUBE DISPLAYS, OR THE LIKE BACKGROUND OF THE INVENTION Information is frequently read out of a general purpose digital computer by converting the digital output thereof into analog signals which are capable of controlling a cathode-ray tube system, so as to form symbols and alpha-numeric characters on the screen of the cathode-ray tube. Several types of such read-out systems exist in the art, and the type with which the present invention is concerned, involves the use of analog wave-form generators which provide varying signal voltages for deflecting the beam of the cathoderay tube, and for selectively blanking the beam, so that the particular symbols and charactersmay be traced on the viewing screen of the cathode-ray tube. This is achieved by applying complex analog wave-forms to the deflection electrodes of the cathode-ray tube, and by employing appropriately timed beam unblanking signals to activate the cathode-ray beam in the tube as it sweeps over portions of the viewing screen, so that the desired characters and symbols may be formed.

In the practice of the present invention, the individual characters and symbols to be produced on the screen of the cathode-ray tube are considered as being composed of a combination of segments common to a plurality of such symbols and characters. The system of the invention, therefore, includes an analog signal generator which is capable of generating various figures, and the system utilizes the figures to synthesize the various characters and symbols. For example, and as mentioned above, the system of the present invention generates four different figures, and these figures are used, in conjunction with appropriate blanking signals, to synthesize the different characters and symbols on the screen of the cathode-ray tube.

In practice, the analog signals corresponding to the different figures are applied sequentially to the cathode-ray tube, and the resulting segments of the symbols and characters to be displayed are positioned on the tube viewingscreen by the application of suitable biasing voltages.

As also mentioned above, the system of the present invention permits each character to be implemented in three draws or less. The system to be described, for example, is capable of implementing a full 96-character code set, and in addition, 65 special characters, a cursor character, and 32 additional special symbols. Moreover, the system to be described is capable of displaying the symbols either vertically or horizontally, and the symbols may be displayed in a variety of selected sizes.

The system of the invention derives its multi-bit digital commands, for example, from a read-only memory which is formated, in the embodiment to be described, into 32-bit words, each word constituting, for example, a separate command. Each command defines a particular draw, as well as the X- and Y-size, theX and Y displacement. and'the segment start and stop position. Each'command also contains, if required, the address of the next command, when multiple commands are necessary to complete a particular character or symbol. Each command also includes a character 6 BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a graphical representation of the four basic patterns generated in the system of the invention, insofar as the illustrated embodiment is concerned;

FIG. 2 is a general block diagram of one embodiment of the system of the invention;

FIGS. 3 and 4 are logic diagrams of an analog function generator which is included in the system represented by the block diagram of FIG. 2;

FIGS. 5 and 6 are logic diagrams of a velocity control circuit, which likewise is included in the system of FIG. 2; and

FIG. 7 is a logic diagram of an intensity control circuit also included in the system of FIG. 2.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENT The system shown in FIG. 2, and which may be designated as a character font generator, supplies unblanking, intensity, and X and Y deflection signals to a cathode-ray tube system 10, so as to cause characters and symbols to be displayed on the screen of the cathode-ray tube. Character positioning on the cathode-ray tube may be provided by a vector drawing system in the display, and which does not constitute part of the character generator and, for that reason, is not shown. The font generator of FIG. 2, as explained above, is controlled by multi-bit commands, which may be stored in a read-only memory. When any particular symbol is to be displaced on the screen of the cathoderay tube 10, the corresponding command in the readonly memory is addressed, and that command is caused to be shifted into a register associated with the memory. Since the memory and its associated register form no part of the present invention, these components are not shown.

The font generator system of FIG. 2, in response to control signals and data in the read-only memory register, constructs characters on the screen of the cathode-ray tube 10 by assembling scaled and displaced parts of the four basic figures, shown in FIG. 1. The four figures are designated alpha, beta, gamma and epsilon respectively. The font generator of FIG. 2 generates the alpha figure in response to a term CGAL; it generates the beta figure in response to a term CGBE; it generates the gamma figure in response to a. term CGGA; and it generates the epsilon figure in response to a term CGEP. The part of a character or symbol on the screen of the cathode-ray tube 10 drawn in response to any particular command in the read-only memory register, as represented by part or all of one of the foregoing figures, is called a draw. One or more draws may be required for any particular character or symbol.

Any particular command in the read-only memoryv is assumed, for purposes of the present description, to

comprise 32-bits. The bits of each individual command are divided into the following fields:

Bits CM00 through CM07 are used to address the next word of the read-only memory, when any particular character or symbol requires more than one draw, and these bits do not appear as inputsto the font generator system of FIG. 2.

Bits CM08 through CM] 1 control the horizontal display deflection of the selected draw pattern.

Bits CM 12 through CM14 control the horizontal scale (dimension) of the selected draw pattern.

Bit CM 15 is not used.

Bits CM16 through CM19 control the vertical displacement of the selected draw pattern.

Bits CM20 through CM22 control the vertical scale (dimension) of the selected draw pattern.

Bits CM23 through CM25 control the starting position of the selected draw pattern.

Bits CM26 through CM27 control the terminating position of the selected draw pattern.

Bits CM29 and CM30 select the desired draw pattern.

Bit CM31 (terminate) indicates that the corresponding draw is the last one of a given character, and this bit likewise does not appear as an input to the font generator system of FIG. 2.

The system of FIG. 2 includes appropriate draw select decode logic 12 which respohds to the bits CM29 and CM30 of the command in the read-only memory register. The decode logic 12 causes the term CGAL, which selects the alpha pattern A of FIG. 1, to be true, for example, under the condition CM29- CM30. The draw select decode logic 12 causes the term CGBE, which selects the beta pattern B of FIG. 1, to be true under the condition CM2'CM30. Likewise, the logic 12 causes the term CGGA which selects the gamma pattern C of FIG. 1, to be true under the condition CM29-Cm. Finally, the logic 12 causes the term CGEP, which selects the epsilon pattern D of FIG. 1, to be true under the condition CM29CM30. Any known logic circuits for achieving the functions described above may be used for the draw select decode logic l2, and, for that reason, the decode logic stage shall not be described in circuit detail.

The system of FIG. 2 also includes a draw counter 14, which, in turn, includes three flip-flops K0, K1 and K2. The flip-flops are connected as a three flip-flop eight-state counter, and the counter controls most of the operations of the system of FIG. 2. Each state of the counter 14 corresponds to a segment of the pattern selected for any particular draw. The counter 14 is normally slaved to the bits CM23, CM24 and CM25 of the command in the read-only memory register, except when the draw flip-flop 16 is set, so that the term NCG- DRAW is false. For the latter condition, the draw counter 14 advances from one state to the next for each pulse received from an advance clock generator 18, which may be in the form of a one-shot multivibrator, such pulse being designated CGADVC. The draw counter 14 advances in binary sequency from one state to the next except for the following conditions:

A. The draw counter does not change state while a beta pattern B of FIG. I is being generated;

B. The draw counter will skip the binary states of one and two when either the gamma pattern C or the epsilon pattern D of FIG. 1 is being'drawn. If states 0, I or 2 of the draw counter 14 are used for the initial position of the gamma or epsilon patterns, the next state of the counter will be state 3. This is used to develop blanking for certain special draws.

The system includes a draw decode logic circuit 20 connected to the output of the counter 14, and this logic expands the binary output of the draw counter 14 to eight lines designated CGLO through CGL7 of unitary code for use in other logic functions.

The advance clock generator 18 supplies a pulse to advance the draw counter 14 at the end of a pattern segment, for the alpha, gamma and epsilon patterns of FIG. 1. The advance clock generator is triggered by selected level detectors included in the block 22. For each operation, the correct level detector in the block 22 or the particular pattern and segment being drawn, is selected at the appropriate time. The selected level detector triggers the advance clock generator 18, so as to generate a clock pulse CGADVC. The level detector consists of eight comparators connected to detect discrete levels of the X(horizontal) and Y (vertical) outputs of an analog function generator (to be described) represented in FIG. 2 by a block 32. The conditions detected at the output terms generated by the level detectors 22 are as follows:

Condition Term (true) X is positive CGX 0 Y is positive CGY 0 X is greater than +l0 volts CG+XD Y is greater than +l0 volts CG+YD X isless than-l0 volts CG-XD Y is less than l0 volts CG YD X is greater than Y CGX Y X is greater than Y CGX (Y) During the beta pattern B, no CGADVC clock pulse is generated.

The font generator system of FIG. 2 includes a terminate decode logic circuit represented by the block 24, and it responds to three binary inputs NCM26, NCM 27 and NCM28 from the command in the readonly memory register to produce eight unitary outputs designated CGMO-CGM7. These outputs are applied to an appropriate terminate control logic circuit designated by the block 26. This latter logic tests for equality of the output from the draw decode logic line CGLO-CGL7 and the terminate decode output lines CGMO-CGM7, for the alpha, gamma and epsilon patterns of FIG. 1. Wen equality occurs, an output CGTNBE causes the draw flip-flop 16 to be reset on the next CGADVC pulse from the clock generator 18. This terminates the draw operation for the particular character or symbol represented by the command in the memory register.

Completely separate terminate logic circuitry is used in the block26 for the beta pattern B (FIG. 1), since the beta generator continues to generate a circular pattern until it is told to stop. Therefore, it is necessary to compare the location of the generator output signal with the terminate decode output lines CGMO-CGM7. This is achieved by comparing the output combinations from the level detectors in the block 32 (CGX 0, CGY 0, CGX Y, CGX (-Y) with the outputs CGMO-CGM7 from the terminate decode logic circuit 24. When a correct comparison is made, a reset signal NCGTBE is applied to the draw flip-flop 16 to reset that flip-flop, and thereby terminate the draw operation.

A problem occurs when the beta generator is required to draw a closed pattern. Due to tolerances, the terminate signal may be present at the beginning of the draw. To prevent this condition, the terminate signal NCGTBE is inhibited until after the end of the first segment of a draw, this being achieved by the output NCGTR of a terminate ready flip-flop in the control logic circuitry of block 26. This flip-flop is reset at the beginning of each draw. The set signal for the terminate ready flip-flop is generated by the logic in block 22 which selects the level detector required to change the state of the clock generator 18 at the end of the first segment of the particular draw.

The system of FIG. 2 includes a busy flip-flop 28. A pulse on C DRAW input line sets flip-flop 28 to cause the term NCBUSY to become false indicating that a draw sequence has started. After a 1 microsecond delay to allow the analog circuits to settle to the start position selected by the command in the read-only memory register, a pulse on the DRAW SET input line sets the draw flip-flop 16 to initiate the draw. When the output of the system of FIG. 2 reaches the terminate position (end of draw) selected by the command in the read-only memory register, the draw flip-flop 16 and busy flip-flop 28 are reset, and the NCBUSY signal becomes true indicating to the control circuits that the draw has been completed.

The system of FIG. 2 also includes integrator gating logic represented by the block 30. When segments of the alpha, gamma or epsilon patterns of FIG. 1 are being drawn, this logic circuit selects the direction of integration for the analog function generator 32 controlled thereby.

The system of FIG. 2 further includes initial position logic circuitry represented by the block 36, and this logic generates eight outputs to enable the integrators in the analog function generator 32 to be properly positioned at the start of any segment of any pattern selected. The output term from the initial position logic, and the corresponding output from the analog function generator 32, are shown by the following table:

Output From A.F.G. 32

The cathode-ray beam of the cathode-ray tube is normally blanked, and the system includes appropriate unblanking logic circuitry 38 for unblanking the beam at selected times. Except for details to be explained, the unblanking of the cathode-ray beam occurs during the time the draw flip-flop 16 is set. An adjustable blanking delay circuit may be included in the unblanking circuitry 38 to compensate for delays in the deflection circuit of the cathode-ray tube 10, thereby permitting the beam position to reach the end of a segment before blanking occurs. During an alpha pattern, draw segment 4 is always blank. Some special blanking patterns may be used to save words in the read-only memory. Two additional outputs originate in the unblanking circuitry 38. An output designated NCGOUTD is used to cause the output CGXC and CGYC from the system of FIG. 2 to go to zero when the system is not busy. The second output NCGIP switches the integrators in the analog function generator 32 into the initial position mode when it assumes zero state.

The system of FIG. 2 also includes character size decoding logic 40 which responds to two input bits 8Z0 and S21 derived, for example, from manually controlled switches. These two bits are decoded in the logic circuitry 40 to provide four character sizes. In order to achieve size control the three logical outputs NCGGl, NCGG2 and NCGG3 from the logic circuit 40 are used to control the gain of the output amplifiers 42 and 44 which couple the system to the horizontal and vertical deflection electrodes of the cathode-ray tube 110. The logic circuitry 40 controls the gain of the amplifiers 42 and 44 by controlling their respective feedback circuits 46 and 48. In this way, four distinct character sizes may be derived as the terms S Z 9 15] SL1 respectivfl assume the conditions SZOSZI, SZil'SZl, SZD'SZI, and SZil-SZI. When the character generator is not busy (NCGOUTD) is false, the smallest size is always selected.

The output of the analog function generator 32 is applied to appropriate amplitude and displacement circuits represented by the block 50. Two inputs from the analog function generator 32, namely CG-X and CG-Y are scaled and summed with the displacement output to obtain the composite current output at CGXN and CGYN. Digital inputs from the command in the read-only memory register control the scale and offset level. As mentioned, X scaling is controlled by the bits NCM12, NCM13 and NCM 14, whereas Y scaling is controlled by the bits NCM20, NCM21 and NCM22.

Character rotation is achieved by the circuit represented by the block 52. The terms NCGRN and NCGRQ are derived, for example, from manual controls. For a horizontally oriented character, the term NCGRN is false, and the two current inputs CGXN and CGYN from the amplitude and displacement circuits are connected to the two outputs CGXCN and CGYCN respectively by two field effect transistors in the character rotation circuit. For vertical character orientation, NCGRQ is false, and the X input CGXN is connected to the Y output CGYCN by a field effect transistor, but the Y input CGYN is switched to the input of an inverting amplifier, and then suitable resistance means at the output of the inverting amplifier supplies the current to the X output CGXCN.

As illustrated in FIG. 2, the output from the output amplifier 42 namely, CGXC, is applied through an attenuator 43 to the horizontal deflection electrodes of the cathode-ray tube 10 to control the horizontal deflection. The output from the output amplifier 44, namely CGYC, on the other hand, is applied through an attenuator 45 to the vertical deflection electrodes of the cathode-ray tube 10 to control the vertical deflection. The UNBD output from the unblanking logic circuitry 38 is used to control the unblanking of the beam in the cathode-ray tube 10 when characters and symbols are being drawn. The system also includes an in tensity control circuit 54 which will be described in more detail with respect to FIG. 7, and which develops an output CIV which'controls the intensity level of the cathode-ray beam so that character intensity will remain constant for all selected character sizes.

The logic circuit detail of the X-channel of the analog function generator 32 for the alpha, gamma and epsilon draws is shown in FIG. 3. The Y channel connections may be identical, except for the substitution of Y inputs and outputs for the X inputs and outputs. The logic diagram for the beta pattern is shown in FIG. 4. When a character is not being drawn, the term NCGIP is false, and the integrator amplifier 100 of FIG. 3, and the integrator amplifiers 200 and 202 of FIG. 4, are connected in an initial position mode. For this mode, the field effect transistors Q11 and Q12 of FIGS. 3 and 4 are in their conductive state, and the field effect transistors Q13 of FIGS. 3 and 4 are non-conductive. The output voltage of the integrator (CG-X) assumes a voltage equal to the current out of the initial position digital-analog converter 203, multiplied by the value of the resistor R31, and is shown in the following table:

True Terrn CG X NCG XP l volts NCG XP volts NCG +7XP 7 volts NCG 7XP 7 volts The voltage across the capacitor C4 becomes the output voltage (CG-X) of the integrator, since the other side of the capacitor C4 is grounded through the conductive field effect transistor Q12. The states of the field effect transistors O18, O19, Q is not important, because the conductive transistor Q12 shunts the current through them to ground.

After the integrator amplifiers I00, 200 and 202 have settled to the initial position value selected by the read-only memory data in the memory register, a pulse on DRAW SET transfers the character font generator system of FIG. 2 to the draw mode, and the term NCGIP becomes true. The field effect transistor switches Q11 and Q12 are now rendered non-conductive, and the transistor switch Q13 because conductive, connecting the integrator amplifiers 100, 200 and 202, and the corresponding capacitor C4 in the configuration to integrate the current from one of the field effect transistor switches O18, 019 or 020.

During any of the alpha, gamma or epsilon patterns, the transistors Q18 or Q19 of FIG. 3 will supply current to the integrating capacitor C4 when either term NCG XI or NCG XI, respectively, becomes false and the term NCGIP becomes true. It might be noted that the term NCGIP controls the field effect transistors O11, Q12 and Q13 in the aforesaid manner to appropriate driver stages represented by the block 102 in FIG. 3, and by the blocks 204 and 206 in FIG. 4. The term NCGB E controls the field effect transistor Q20 through a driver 104 in FIG. 3, and through drivers 208 and 210 in FIG. 4. The term NCGBE is always true except when a beta pattern is selected. Therefore, the field effect transistor Q20 will not supply current to the integrating capacitor C4 for any of the alpha, gamma or epsilon draws.

The term NCG XI controls the field effect transistor 018 through a driver 106 in FIG. 3, and through a driver 212 in FIG. 4; whereas the term NCG XI controls the field effect transistor 019 through a driver 108 in FIG. 3, and through a corresponding driver 216 in FIG. 4. Likewise, the term NCG YI and NCG YI control similar field effect transistors Q18 and Q19 in the Y channel of FIG. 3 and in the Y channel of FIG. 4 through drivers 214, 218. The analog function generator outputs CG X and CG Y are therefore made to trace the alpha, gamma and epsilon characters of FIG. 1, as the draw counter 14 changes states and controls the integrating logic terms NCG XI, NCG XI, NCG YI and NCG Yl through the decode logic circuits 20 and through the gating logic circuitry 30.

Wen the term NCGBE is false, the X and Y integrators are connected in a closed loop with a pair of imaginary poles, in order to trace the beta figure. Then, undamped oscillation will begin when the generator system of FIG. 2 is switched to the draw mode by the term NCGIP becoming true, and this oscillation will continue until the term NCGIP again becomes false. The two variable gain amplifiers 220 and 222, and the inverter amplifier 224 are included within the circuit of FIG. 4. Two velocity inputs CGXBV and GCYBV, introduced to a balancing circuit and velocity amplifier 230 in FIG. 4 control the instantaneous frequency of oscillation by changing the gate voltage of the field effect transistors Q1 and Q4 of FIG. 4, and thereby, the gain of the two variable gain amplifiers 222 and 220. The function of the velocity inputs will be described subsequently herein.

The two output amplifiers 42 and 44 of FIG. 2 are inverting amplifiers. These amplifiers receive input currents supplied by the outputs CGXCN and CGYCN of the character rotation circuit 52, and they generate the final outputs CGXC and CGYC of the font generator systems. The feedback networks 46 and 48 of the respective amplifiers 42 and 44 control the character size, according to the state of the terms NCGGl, NCGG2 and NCGG3 derived from the character size decoding logic circuitry 40. The two attenuators 43 and 45 supply the X- and Y-deflection outputs for the cathode-ray tube 10, in response to the outputs'CGXC and CGYC from the output amplifiers 42 and 44.

The alpha, gamma and epsilon velocity control circuit of FIG. 5 supplies the terms CG VEL and CG VEL through respective resistors R36 and R38 to the field effect transistors Q18 and 019 of FIGS. 3 and 4. The beta velocity control circuit of FIG. 6 supplies the beta velocity control voltage to the circuit 230 of FIG. 4. These velocity control circuits of FIGS. 5 and 6 function to maintain the spot velocity of the cathode-ray tube 10 of FIG. 2 constant as it travels across the screen of the cathode-ray tube 10 regardless of the setting of the scaling inputs from the read-only memory. Simply stated, the cathode-ray beam spot velocity is held constant by increasing the output rate of change of the integrators of the analog function generator 32 in an inverse ratio to the scale setting in effect at each instant of time. For all the figures of FIG. 1, this is achieved by increasing the source voltage supplying the current to the integrators as the attenuation increases. The beta pattern velocity control circuit of FIG. 6 is different from the alpha, gamma and epsilon velocity control circuits of FIG. 5, as will be described in some detail.

With respect to the alpha, gamma and epsilon velocity control circuit of FIG. 5, the bits NCM12, NCM13, NCM14, NCM20, NCM21 and NCM22 of the command in the memory register control the setting of two velocity digital-analog converters 300 and 302 in FIG. 5. The digital-analog converter 300 serves as the X scale, and the digital-analog converter 302 serves as the Y scale. The digital-analog converters constitute the feedback paths of the CG VEL amplifier 308 (-A). The terms NCGXVC and NCGYVC from the integrator gating logic 30 connect either one or both of the digital-analog converters 300 and 302 into the feedback path of the amplifier 308, depending on whether the integration is X or Y, or both X and Y, at any particular instant of time. The control is achieved through respective drivers 304 and 306 and respective field effect transistors O17, O18.

The CG VEL amplifier 308 has a constant current input through the resistor R1 which is connected to the positive terminal of a l5-volt unidirectional source. Therefore, the CG VEL output from amplifier 308 will change in inverse ratio to the scale setting of the pattern segment being drawn. The CG VEL amplifier 310 is actually an inverter amplifier (-1) which inverts the CG VEL output. Both outputs CG VEL and CG VEL are used as the source voltage for the integrators CG X and CG Y of FIGS. 3 and 4, as illustrated therein.

The beta pattern velocity control circuit of FIG. 6 responds to two terms CGBDX and CGBDY of the analog function generator 32 and which are respectively proportional to the X and Y integrator rates of change. The circuit of FIG. 6 includes an X velocity scaled digital-analog converter 400 and a Y velocity scaled digital-analog converter 402. These converters respond to the inputs NCMl2-NCM14 and NCM20-NCM22, respectively, from the read-only memory register.

The terms CGBDX and CGBDY are applied to the digital-analog converters 400 and 402 in FIG. through respective inverters 404 and 406, the inverters being shunted by diodes CR1 and CR2. The digital-analog converters 400 and 402 first generate the magnitude of the rate of change for each of the X- and Y-axes at the cathodes of the diodes CR1 and CR2; and then scale the magnitude proportional to the scale setting, to generate two outputs CGXBV and CGYBV at the output of respective amplifiers 408, 410, these latter outputs being proportional to the X and Y components of the spot velocity of the cathode-ray tube 10. These amplifiers include respecfeedback resistors 33 and 34, as shown.

The two signals CGXBV and CGYBV from the amplifiers 408, 410 are combined in a vector summing network in the circuit 230 of FIG. 4, and are comprised of resistors R13, R14, R and diodes CR3 and CR4, the resulting current output approximating the vector sum of the two signals. The current output from the vector summing circuit is summed at the input of the beta velocity control amplifier 412 in block 230 with a reference current derived from the positive l5-volt terminal through a resistor R11. The output of the beta velocity amplifier 412, that is, the output of the block 230 of FIG. 4, controls the gain of the variable gain amplifiers 220 and 222 of FIG. 4 through field effect transistors 04 and 011 so that the spot velocity represented by the output of the vector summing circuit is always equal to the reference value derived through the resistor RlI. It should be noted that the outputs 'of the variable gain amplifiers 220 and 222 of FIG. 4 are the inputs to the beta velocity control circuit CGBDX and CGBDY.

The function of the intensity control circuit 54 of FIG. 2 is to supply an output voltage CIV proportional to the character size being generated. This circuit is shown in more detail in FIG. 7. As shown in FIG. 7, the terms NCGGI, NCGGZ and NCGG3 derived from the character size decoding logic circuitry 40 of FIG. 2 are applied to digital-analog converter 400. These terms produce different outputs from the digital-analog converter 400 by selecting appropriate feedback networks for an amplifier 402 in the intensity control circuit, the selected feedback network corresponding to the character size being generated. The input signals CG IS and CG IS are connected through respective diodes CR5 and CR6 to a potentiometer R39. The potentiometer R39 is connected to the input of the amplifier 402 through a resistor R38. The output signal CIV is derived from the junction of resistors R33 and R32 connected between the output of the amplifier 402 and ground. The potentiometer R39 is adjusted to balance the intensity of the characters to the graphic structures drawn by the vector generator.

The invention provides, therefore, an improved character font generator system which responds to commands derived from a read-only memory, for example, to cause a display device, such as a cathode-ray tube, to be controlled in accordance with predetermined draws so that various selected symbols may be displayed by the device.

It will be appreciated that while a particular embodiment of the invention has been shown and described, modifications may be made, and it is intended in the following claims to cover all modifications that come within the spirit and scope of the invention.

What is claimed is:

l. A character font generating system responsive to fields of a multi-bit binary digital command, and comprising: analong function generator circuit means for generating analog output signals representative of a plurality of predetermined display figures; draw select decode logic circuitry responsive to the binary bit values of a particular field of said command for introducing a first control signal to said analog function generator to condition said generator for the production of an analog output corresponding to a selected display figure; control circuitry responsive to the binary bit values of another particular field of said command for introducing a second control signal to said analog function generator to cause said generator to produce an analog output signal representative of at least a part of the selected display figure for which said generator was conditioned by said first control signal; cathoderay tube display means having beam deflecting elements coupled to said function generator and responsive to said analog output signal to produce a particular deflection of the cathode-ray beam in said tube; and blanking control logic circuitry coupled to said decode logic circuitry and to said control circuitry and responsive to said first and second control signals for generating blanking control signals in timed relationship with segments of said analog output signal generated by said function generator, and coupled to the cathode-ray tube for applying said blanking control signals to said cathode-ray tube.

2. The combination defined in claim I, in which said control circuitry includes a binary counter and clock generating means coupled to said counter. for causing said counter to step from one state to the next to control the introduction of said second control signal to said analog function generator.

3. The combination defined in claim 1, and which includes terminate logic circuitry responsive to the binary bit values of another particular field of said command and to the analog output signal of said function generator to terminate the operation of the system when the analog output signal of said function generator corresponds to a completed display figure.

4. The combination defined in claim 1, and which includes output amplifier means coupled to said analog function generator for determining the amplitude of the analog output signal produced thereby, and size control circuitry coupled to said output amplifier means and controlling said amplifier means to different levels in response to predetermined inputs so as to select different sizes of the aforesaid display figure.

5. The combination defined in claim 1, and which includes scaling circuitry coupled to the output of said function generator and responsive to the binary bit values of further particular fields of said command for controlling the amplitude of the analog output signal produced by said function generator.

6. The combination defined in claim 5, and which includes velocity control circuitry responsive to the binary bit values of the particular field of said command controlling said scaling circuitry and coupled to said analog function generator to control the integration rate therein so as to change the output rate of change of the analog output signal produced by said function generator in an inverse ratio to the amplitude setting of said scaling circuitry.

7. The combination defined in claim 1, and which includes rotation control circuitry coupled to the output of said function generator and responsive to predetermined input to determine the orientation of the display figure represented by the analog output signal of said function generator.

8. The combination defined in claim 1, in which said function generator may be conditioned by said first control signal to produce an analog output representative of a circle. 

1. A character font generating system responsive to fields of a multi-bit binary digital command, and comprising: analong function generator circuit means for generating analog output signals representative of a plurality of predetermined display figures; draw select decode logic circuitry responsive to the binary bit values of a particular field of said command for introducing a first control signal to said analog function generator to condition said generator for the production of an analog output corresponding to a selected display figure; control circuitry responsive to the binary bit values of another particular field of said command for introducing a second control signal to said analog function generator to cause said generator to produce an analog output signal representative of at least a part of the selected display figure for which said generator was conditioned by said first control signal; cathode-ray tube display means having beam deflecting elements coupled to said function generator and responsive to said analog output signal to produce a particular deflection of the cathode-ray beam in said tube; and blanking control logic circuitry coupled to said decode logic circuitry and to said control circuitry and responsive to said first and second control signals for generating blanking control signals in timed relationship with segments of said analog output signal generated by said function generator, and coupled to the cathode-ray tube for applying said blanking control signals to said cathode-ray tube.
 2. The combination defined in claim 1, in which said control circuitry includes a binary counter and clock generating means coupled to said counter for causing said counter to step from one state to the next to control the introduction of said second control signal to said analog function generator.
 3. The combination defined in claim 1, and which includes terminate logic circuitry responsive to the binary bit values of another particular field of said command and to the analog output signal of said function generator to terminate the operation of the system when the analog output signal of said function generator corresponds to a completed display figure.
 4. The combination defined in claim 1, and which includes output amplifier means coupled to said analog function generator for determining the amplitude of the analog output signal produced thereby, and size control ciRcuitry coupled to said output amplifier means and controlling said amplifier means to different levels in response to predetermined inputs so as to select different sizes of the aforesaid display figure.
 5. The combination defined in claim 1, and which includes scaling circuitry coupled to the output of said function generator and responsive to the binary bit values of further particular fields of said command for controlling the amplitude of the analog output signal produced by said function generator.
 6. The combination defined in claim 5, and which includes velocity control circuitry responsive to the binary bit values of the particular field of said command controlling said scaling circuitry and coupled to said analog function generator to control the integration rate therein so as to change the output rate of change of the analog output signal produced by said function generator in an inverse ratio to the amplitude setting of said scaling circuitry.
 7. The combination defined in claim 1, and which includes rotation control circuitry coupled to the output of said function generator and responsive to predetermined input to determine the orientation of the display figure represented by the analog output signal of said function generator.
 8. The combination defined in claim 1, in which said function generator may be conditioned by said first control signal to produce an analog output representative of a circle. 